IP核的使用有什么要求吗

张翔10

刚接触Verilog不久，需要做个FPGA解二阶微分方程。
我用欧拉法解得，但调用IP核总是出毛病
比如
+ z1 j3 D6 [, c% [  M/ lError (10170): Verilog HDL syntax error at Eeler.v(22) near text "add_sub_inst";  expecting "<=", or "="
7 |. X% i/ E4 K/ w' [9 y$ mError (10149): Verilog HDL Declaration error at Eeler.v(25): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(26): identifier "add_sub_inst" is already declared in the present scope
8 B, h# m* q4 w6 t/ S: P" SError (10149): Verilog HDL Declaration error at Eeler.v(27): identifier "mult_inst" is already declared in the present scope
7 Y; u' h9 G/ o& C- [3 v  D% nError (10149): Verilog HDL Declaration error at Eeler.v(28): identifier "add_sub_inst" is already declared in the present scope
9 [0 y% `4 M. T4 J% a5 n- v/ AError (10170): Verilog HDL syntax error at Eeler.v(30) near text "$display";  expecting "endmodule"
) B2 w9 `) k+ I) x3 @1 MError (10759): Verilog HDL error at Eeler.v(30): object x declared in a list of port declarations cannot be redeclared within the module body
6 o$ b6 e! r- @( t) N1 ~Error (10759): Verilog HDL error at Eeler.v(30): object y declared in a list of port declarations cannot be redeclared within the module body
- o  B0 p( H8 X" }" DError (10759): Verilog HDL error at Eeler.v(30): object z declared in a list of port declarations cannot be redeclared within the module body
Error (10170): Verilog HDL syntax error at Eeler.v(30) near text ")";  expecting ";"
Error (10112): Ignored design unit "Eeler" at Eeler.v(1) due to previous errors
编的源程序这样
module Euler
(
input wire           clk,
  o7 E- r' Z2 }; a) K* x; y, ^input wire    [31:0]   x,      //定义输入量，单精度32位浮点数
7 X# j; Z+ C$ q0 [4 b+ u3 U% L  k, Iinput wire    [31:0]   y,
input wire    [31:0]   z,
, w# M4 A, P; n# y1 j4 Q. M3 J- Sinput wire    [31:0]   h,
$ I8 l- U# P( v0 L9 g9 ]) Loutput wire    n1
8 ]! ?9 f6 m; Q( J& L1 e5 D" ^( e);
% v9 m5 l* @) Q1 H! l, \( F


. [" _* L4 ]( Y1 {6 @3 v" j( G0 e
reg[31:0] z11;
reg[31:0] z1;
7 i# t9 L) i% n/ p% Q' areg[31:0] y11;
reg[31:0] y12;
1 X; I9 P0 d6 a' Zinteger n;
  f0 q; R3 y- ~# B- V3 u3 t( z

initial
6 A- o3 Z9 i3 b  X //开始迭代
for (n = 0; n < 10; n=n+1)      
add_sub add_sub_inst( .clock ( clk),  .dataa ( x ),.datab ( h ),.result ( x ));
mult mult_inst( .clock ( clk ),  .dataa ( x),.datab ( z ),.result ( z11 ));            
add_sub add_sub_inst( .clock ( clk),  .dataa ( z11 ),.datab ( y ),.result ( z1 ) );      
' h$ \1 R3 _9 Z" z  B8 mmult mult_inst( .clock ( clk ),  .dataa ( h),.datab ( z),.result ( y11 ) );         
add_sub add_sub_inst( .clock ( clk),  .dataa ( y ),.datab ( y11 ),.result ( y ) );   
mult mult_inst( .clock ( clk ),  .dataa (h),.datab ( z1 ),.result ( z12 ));         
add_sub add_sub_inst( .clock ( clk),  .dataa ( z ),.datab ( z12 ),.result ( z ) );
4 O- G& j) X$ a! m) W$ a- H
, f8 ^  O* h$ J
$display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
; n! x6 X5 x  X8 G* }0 [) G+ b! u6 dendmodule
想问一下，是IP调用有问题吗？还是IP核不能在循环或函数里调用

xiaozhubanna

用另一种方式也有问题
module Euler
(
input wire           clk,
" [* n( B# a# ^$ a4 y5 V8 C( Q9 K5 `input wire    [31:0]   x,      //定义输入量，单精度32位浮点数
. a0 x( _# T3 D* @1 B9 I% l) ~input wire    [31:0]   y,
input wire    [31:0]   z,
input wire    [31:0]   h,
output wire    n1
);


function   [31:0]   g;//加法器函数
  input   reg   [31:0]   x;
  input   reg   [31:0]   y;
9 i& d. f6 p$ L- L% T) x8 r          reg   [31:0]   z;  
8 F8 z5 `7 c5 b( s. I3 y; obegin         
: o8 s# S% c7 f* u, Oadd_sub add_sub_inst(
   //调用浮点数加法IP
.clock ( clk),
8 J9 j/ p! d) a9 z.dataa ( x ),
% o4 ]$ c% _) t6 |1 Z% o5 a# v) W& A.datab ( y ),
.result ( z )
. r  C1 g8 X; @: ^3 W8 i    );
: Q3 J. U3 Q+ d& }9 Z$ {# v    g    =    z;
end
; T9 r1 w  n9 Y' x$ Fendfunction
2 B% B% e$ J# G8 z: r1 J
$ Q, h8 E& {7 B) I3 i

1 t! e& {8 N0 |3 z2 u
function[31:0]f;       //乘法器函数
  input reg [31:0]x;
; X( r0 M- B7 h. |. n7 V  input reg [31:0]y;
   reg [31:0]z;
begin   
mult mult_inst(
  //调用浮点数乘法IP
! _- F$ s- [) g1 v, G.clock ( clk ),
.dataa ( x),
.datab ( y ),
8 L; v; _: r5 J! r1 Z.result ( z )
7 d& y. e8 j8 t4 x( R: b );
6 W+ n5 D5 d0 I: ^8 F# l. \; V* K  f = z;
end
endfunction

2 f. I, f# b5 n& H! I' ?
1 \9 r: s  {# p9 g1 t- M7 Sreg[31:0] z11;
reg[31:0] z1;
% F2 `, _- F" C8 ~1 h5 vreg[31:0] y11;
reg[31:0] y12;
integer n;
2 t7 r9 G  d2 w  T- d4 w

initial
begin
! D# l7 H* f/ }/ w9 n( w                     //开始迭代
6 e% e3 Q" Z5 W' Sfor (n = 0; n < 10; n=n+1)
9 T9 z, n+ N* i( T  N# M# K      begin
        x   = g(x,h);
        z11 = f(x,z);
        z1  = g(z11,y);
        y11 = f(h,z);
        y   = g(y,y11);
* d3 T  W, y; x. z        z12 = f(h,z1);
        z   = g(z,z12);
       $display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
8 E, m1 W0 u0 V8 L! G      end
end
' w$ s0 t8 s+ K2 xendmodule
错误报告是
Error (10170): Verilog HDL syntax error at Eeler.v(16) near text "(";  expecting ";"
+ {( R7 e* E# H9 j4 Y3 x+ w7 |! ZError (10170): Verilog HDL syntax error at Eeler.v(33) near text "(";  expecting ";"
- C5 C( N8 y( A+ UError (10112): Ignored design unit "Euler" at Eeler.v(1) due to previous errors