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27号补丁修复的BUG较多！
; p" M$ p6 D5 V4 ~百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
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0 H; I. I7 ^5 dDATE: 04-25-2014 HOTFIX VERSION: 027
% L, r0 _% e: y5 ^8 W===================================================================================================================================
, }$ I' V& ^" D4 g8 X* c# H9 N8 x( dCCRID PRODUCT PRODUCTLEVEL2 TITLE% C* U+ i' b5 J. e7 e! J+ s' x
===================================================================================================================================9 Q! v7 e2 A4 d1 R" l
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
; D- A* Z; `3 S4 n481674 allegro_EDITOR pads_IN No board file saved from pads_in6 O0 n6 t( A8 ]+ q6 _' @0 {
982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
1 `1 F; V7 [6 d2 w9 ]5 L4 p1012783 FSP OTHER Need Undo Command in FSP
6 p1 }: ]' E& H; Z1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
9 a5 \! }8 f) Z p/ r+ V1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
( [. H8 p, v9 A1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
8 `( J2 O1 n1 F" |1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups! O9 P) d5 ]0 K& U% w4 n
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
/ B, K; l0 d' m& r; m& p1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command. F D" k4 P4 Y( B
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode+ M. `* G$ y6 w( I. T1 ]- c0 Z
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
* S; h: J) B/ T, |% f1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
+ @5 c. y3 e/ h; `$ ^1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings; ?* J+ v0 \( a: B+ _$ J) `
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.7 m- Q j( ]7 h7 F
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
4 O/ R$ r9 s- z% ~) G7 ]& R* L9 ?; P1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.* x% F( S; M# Z; g0 o
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
- F( {% O% p, t' Q% n1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime, e8 ]0 F3 R, J$ d5 T" A
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.& l2 S' a" ^( l, U
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol0 J. J- u8 e( o& S& R0 p
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed7 d3 n! s6 g" p7 d
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape6 w) S# q2 |8 u2 { O; f
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers( V2 S5 P4 V- k$ ~" _7 \* }' H
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?! T( V$ f7 z9 [" X) @% v& I( u
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.) |7 ~. Y% y. t7 m: Z, ]+ B
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
0 b L8 [' @ N1 C( w1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
6 z5 b* f! o( s: I1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
% \3 I$ X) v X/ T: J) j$ l- y# Z1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
+ _ f) U+ J0 M5 w6 q1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.* `, E3 w _/ ~. k0 s
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes0 H: P2 U1 t3 f9 e7 }, n. B4 A
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux! h0 N' o/ @7 K! s
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
4 B; X; P6 Z# R* a; r3 Y1221182 ADW TDA Team Design with SAMBA, t0 u/ I: [6 |
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
1 c" i% {4 s3 b7 B8 j c' [; k1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
) x( t( z) E& R; R. N1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?) k2 Z. Q# M$ i
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts3 w S& E! {2 f$ r3 N
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms2 T9 J5 G% v1 t, [! r3 Q
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
8 i2 z5 K* P5 A+ @- e1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
, H& K- ?. R0 q& G6 ^% V1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.0 d0 h: I/ T9 A# k- b
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path* G0 o$ G! k+ M" N |
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin( k" q3 l1 x; K# Q% R
1225494 CAPTURE DRC Different DRC results for Entire design and selection: S' r5 D: W! c
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property* q! S9 e- G0 ^1 m1 }; M. i
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
4 K- _: C* ]2 i( N( l6 D( n1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
, ^! w4 ?. \7 A$ [/ W, d% A6 f6 F1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal3 v6 h: K6 b Q# v- N
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
0 J, D# H8 \7 ~6 H0 n8 \1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
1 ]5 i, r: e7 G4 x# V1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1 p# K9 G% a! I/ t4 E% ]1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
- y( q/ {4 E: {. J" `1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
* Y; o+ W* M$ ?( A) h$ A1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
) N5 A) @- o M& k/ f1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
! ?* ?4 b; b, B6 N1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection R9 m# G+ r( u
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time." H8 `) f2 B& M1 x
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.% a! A' P: `" c+ L7 [( S5 R% p+ C
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
9 {/ L# c: R! O9 }0 `/ S% F1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
8 A6 _. O! R2 i) ~1 h$ M3 J1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
* p1 \9 R) H$ s' G2 K' `1230432 CONCEPT_HDL CORE No Description information in BOM' R0 ^) m9 s$ ^5 V
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
0 ^3 I% A' Q, h) p3 a2 s1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files2 L G9 |! t9 d! T! X/ V" h
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
7 i, V3 S, L$ S1 W5 ~, D4 |1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets% Y3 n8 C M9 A; R; x
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
8 a+ C2 y. c$ p! \( ~# F4 u" W1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
/ w& u) E( b2 |! y( @5 i1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
; r: r: G# w- b1 b- a0 r' r- y) V1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
h5 n" K0 D2 e6 f& l8 g# j1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files, `* |: `: ?' \; S- j& L
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy" y/ \. n2 b4 N- ]" `
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
; N* K1 D& i- k# B5 f1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect% i* @6 c5 l' T0 }
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
) [" D6 V8 I( D& }2 S- N1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic5 M2 A8 a2 O5 U& W" `3 j4 m
1236161 CONCEPT_HDL CORE Import Design shows the current project pages* g: o5 m8 ?: \- z
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.; i1 l5 ]# Y; [( r2 A
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
$ S! E0 t5 ^' p4 k `1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file$ l7 @% T ?. b. e
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape2 w# b* M+ G/ ]2 H
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
p& _# e% V% e# e: c1 w* |1236781 F2B PACKAGERXL Export Physical produces empty files
2 V; h* R' H. o" t: s1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run/ ~. {( W2 n1 ?* t1 s0 l
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command3 p1 f+ Q% T9 \& P: A% u/ |" X* x" }
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
7 W: W4 V5 d8 A! S' j i9 @1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
6 j0 M3 ~, c3 |% h: m1238852 CAPTURE GENERAL signal list not updated for buses5 {- J6 n' w& `/ V1 x) j
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
2 _$ \* l+ y+ _6 @) u1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
2 u$ \9 o2 ]0 a, A# i% T {1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE) r8 [' ^! D/ r7 T
1239763 PSPICE PROBE Cannot modify text label if right y axis is active& y& W: E3 e: d$ l
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
: S, ]) r: D& E6 |* Y1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.9 r5 X5 J4 {& f) r4 ~- k4 ~
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing" n" o) V" | E
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
" G! N8 K. D7 ]8 ~1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
$ V% c8 g7 C, f6 {1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
; B0 g7 p7 b! [& J1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
0 N$ V1 A% ^, [1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
% ]9 M9 f Q' G& v1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
5 w) j* e) ~7 j1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
& B% n5 b% ^# E1 N1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
! R z$ E# X. s8 O1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
0 e% t' `5 Y7 J7 K3 T7 y+ H1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer$ J: a; ^& ]4 g* I9 M1 n0 P
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
3 t5 H2 s( h) Z7 l1 _1243609 CONCEPT_HDL CORE autoprop for occurrence properties
/ K1 s! W/ A8 V; a: j/ c1 j1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
4 g0 h# L' O9 g7 Y; l& N1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
$ c1 W9 q, C9 g8 }5 z ]1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring" N- t7 Z" a% F7 z+ h8 V
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder9 K& M$ z# I, h! F7 @' W
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
1 T+ z% a; w% ]8 b+ D# G, f1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design9 V5 w6 `- r5 z
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
1 i* L/ a3 _# x: H1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character/ C; k* _* t5 h0 V/ i1 B6 y
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters8 {8 F' @3 Q' h2 L/ j$ M2 z
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown5 b7 [ `+ W, {5 z' t
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number8 \' o+ {' [: S+ c5 y: J* s
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
4 X1 j, j, a' b- D1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
. n; S4 }! M/ W. C4 b3 R" A$ l1247462 CONCEPT_HDL CORE Text issue while moving with bounding box: w# Z" ?4 j6 b8 u
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered( e' J, M4 X% ^, r+ e% t
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components d3 k% G7 @$ W" P, y7 r3 b
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
8 ^# _7 k1 t+ M- i6 t1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.: e9 F( p1 [+ }* g* v0 |
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint" A$ w! Z7 M; m7 W
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly: k5 ^# f; E& K* f0 @0 M. t
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it." r: G8 |4 N: w8 @3 x2 C
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies3 w! H m( A# Z! P, R5 U$ }
1253424 SCM SCHGEN Export Schematics Crashes System Architect; _: w) [) r/ U( Z
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
8 [* S. M @* ?8 ` W# x o1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing; Z+ o' s2 ~7 Z' O4 O" F" x
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
. h( s( Z* {9 W1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error9 r; G1 G n# K7 Y- G
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.! V( U6 m( S; ~4 S
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation) a b# B8 Z2 o s: R
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects3 P& A Y" O% l0 F# g- u" f* ^
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
/ I- V3 \ U" A, J& z1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided7 ~2 |2 Y( C; `- y, A. w3 x4 {+ o
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
' n. _5 X2 z* I6 l# o- F1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
: s0 [& i2 L& M- f3 k1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
9 N; {2 Q/ w, |: \0 @$ |1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library+ N, f7 E/ t& g2 D3 I9 D6 B
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long& w) z. W; g' n' ~, \. X6 u
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
1 S" {1 s# w$ o% V- r/ ~1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
; [8 L2 A6 N3 |: ~1258029 APD WIREBOND The bondwire lost after import the wire information
/ B, U) e5 V5 X3 u1 G1258979 APD NC NC Drill: There is difference of number of drills.; |% ^, [1 V- j2 D7 n. U y
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
" Y- H" a$ @7 B; T; Z ?, k1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.; @) ^1 h: N8 E$ r* Q
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
4 h, P9 [8 ?, c* z* y r' O9 j ]1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines5 g" m( P, s w4 o1 z/ l* j
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void/ T ~9 n, |9 {% D" v
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
g5 c3 `( s2 ]4 h; }' S ]) s, S! }# T& ]% C/ a7 \7 f2 R
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