SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe

cesc

27号补丁修复的BUG较多！
百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy

* v" H: b/ X* _* v* H% {DATE: 04-25-2014   HOTFIX VERSION: 027
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# ~! Z; H, p. s2 O- T7 s! uCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
3 P9 B  S$ ?( i6 r9 T) w1 D1 ^1 i481674  allegro_EDITOR pads_IN          No board file saved from pads_in
9 b/ T6 H: L) H982929  allegro_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
1012783 FSP            OTHER            Need Undo Command in FSP
1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
1072673 pcb_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
1073231 CONCEPT_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.
( Q" I# Z$ _0 Q: D1 @. m; ^1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings
1185575 SIP_layout     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
/ P: h- S% [; l$ @( o1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
3 ]* D. v( b1 v: S1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates
6 t4 h/ [9 M2 z. j3 R! g8 G5 @1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime
' B1 E; ^' h1 ]! u# o5 Q" ?1208478 PSPICE         PROBE            Attached project gives overflow error with marching ON.
1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
+ ]+ |* O8 B+ p$ D# H! Y1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
/ E2 i2 J+ w0 g8 W4 t1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?
1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.
  y2 v& {0 ^+ E4 u. f1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values
1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging
; Y0 X2 |/ Y* p* G) K( N1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
) p- K' |9 J" Q1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
' l! z1 s8 l/ S  Z8 x1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes
2 h' A3 A8 s8 }  [: o* |5 R1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux
2 n5 m" p% O9 z- V1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
1221182 ADW            TDA              Team Design with SAMBA
1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair
( N5 p) b2 J( |$ i3 Z1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened
8 t  k5 f0 F& l# {; }( ?+ i- s1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts
1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
) e$ x$ w# |& l1 u/ I  I! S% P1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor
2 N1 n  `+ @/ F5 L: v9 W, [8 M1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path
' P% o4 R, \* g7 a! O, h1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
* `. x0 `: s4 I1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
6 Z) |  x/ e1 i1 k  \% x/ w1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property
' Y! u, W: `' ?7 ^. U' `6 p0 o3 Z- ^1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet
( F2 k& M9 W( J) }- C1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal
! h2 R; O" l/ r4 T( N" T1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
" }/ u4 t: n, ^. g1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration
1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case
7 E( h6 C0 _+ z+ f  E( t8 {1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
9 O' s: j( j+ f1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
# G9 g) v4 r) {/ V+ _1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
0 X4 j' n6 T* Y* J* H/ f7 z3 J% z1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
1230432 CONCEPT_HDL    CORE             No Description information in BOM
# h- Y2 a6 X- S) n. V1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes
( z# A: c. M: ~/ W1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files
+ R" g6 \3 Z" A. J1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets
1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
8 y) L* U, w$ ^; r/ ]7 l  [+ ?1232100 CONCEPT_HDL    SKILL            Unable to execute the SKILL commands in viewer mode
1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical
1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
3 I; m0 o' Q4 g: S, b* w1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
8 O8 B0 @" I6 i1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved
1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect
$ x& ~, d$ \: G' x9 Y9 L2 B1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set
1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages
1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.
1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
" v% }0 w- P$ T9 b, m7 g6 K0 S8 p1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
6 m$ l+ H- @) d- k1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
2 @# R& ^# |1 D- V) g1236781 F2B            PACKAGERXL       Export Physical produces empty files
1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition
1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.
( q7 ?$ V$ J! `, @/ q" o" l: o1238852 CAPTURE        GENERAL          signal list not updated for buses
7 H+ _  ]2 x5 b0 M1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes
1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE
. ]% S* G3 |- C1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
$ M$ n5 }- v9 d8 q/ R- @# o' z* N1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
* e9 g# E0 b! ]+ Q+ }8 `: Y3 w1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file
& c( ^/ @' P5 w+ i0 D1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable
$ w( X5 g! f+ p1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
- i0 s5 h7 c( t5 P5 r6 c& x1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working
  ^  H" J" e6 D1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.
6 F: x' s8 I1 j1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning
$ |7 \6 x$ z* I1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side
1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
1 |8 i, Q3 u# S* u* i, ?1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
$ Z, A. _1 I) {5 N3 `- k1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring
% ?* p" b! c& U8 i1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder
) G7 q; R% {' _1 c, R8 G0 H1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
8 F; `& |; T' S: t7 W1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design
9 A% K4 \( U% w! U, }1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
$ }2 X* {& f0 y% ]7 A1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL
1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained
1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
( Z" k0 M5 V/ a- |' }1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components
/ S, R0 }3 e- X5 D3 c1 R1 i1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
1 d( i1 V7 A1 u' J+ P: l4 n1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
( i1 `" ]8 B" X, c/ y' \: M8 Q. a4 s1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
- a! F! q4 @9 {1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
7 a) U6 x, U) {1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
4 O. t$ W7 H# s1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error
1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
) M5 L2 e' F! S( S0 f6 B( m, ]1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation
+ F7 W4 ^7 V$ n. Y' _1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
+ ~" L5 F1 v" n" g4 m1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode
5 N8 ], }! K  X/ c; V4 L6 f1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
, a( `7 v2 G6 m( E2 w2 R. ~7 S9 F1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
0 M, D5 o2 @+ z' S/ n1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
: ]: a- M$ g! a- n- m1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
  ?0 m  E0 N1 f: _0 k1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash
1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time
! P* ]7 L6 v; p' e1258029 APD            WIREBOND         The bondwire lost after import the wire information
1258979 APD            NC               NC Drill: There is difference of number of drills.
0 j4 ?1 P% F* h1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
1 _0 [4 m: w7 l: Q5 `; b1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
7 F, K* }8 [) n' |1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines
1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
  y2 x# U3 u2 }  u- v1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
3 c2 H; t) W; i# c

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