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AD导出的第三方网表，经过网表转换工具输出.txt格式，非法字符已改；dev、pad、psm文件库路径均已指定无误，但是在allegro中导入第三方网表后staus状态未更新，可放置器件仍为零。log文件也没看出啥问题。求大神指导一下额
 
(---------------------------------------------------------------------)
( )
( Allegro NETLIST IN Log File )
( )
( Drawing : high voltage switching power.brd )
( Software Version : 17.4S031 )
( Date/Time : Mon Dec 12 21:47:47 2022 )
( )
(---------------------------------------------------------------------)
Mon Dec 12 21:47:47 2022 Page 1
Netlist File: 'D:/Cadence/fan yi/practice/high voltage switching power/SCH/hig~
hPower.txt' Physical Design File: 'high voltage switching power.brd'
===========================================================
_PACKAGES
CC509_5 ! CC509_5 ! ; C1
CE2050 ! CE2050 ! ; C2
CE50130 ! CE50130 ! ; C3
C0805BSM ! C0805BSM ! ; C4
C10013_4 ! C10013_4 ! ; C5
C0805BSM ! C0805BSM ! ; C6
C0805BSM ! C0805BSM ! ; C7
C508_3 ! C508_3 ! ; C8
CE3580 ! CE3580 ! ; C9
C508_5 ! C508_5 ! ; C10
C508_5 ! C508_5 ! ; C11
CC509_5 ! CC509_5 ! ; C12
CC509_5 ! CC509_5 ! ; C13
C10013_4 ! C10013_4 ! ; C14
C0805BSM ! C0805BSM ! ; C15
C0805BSM ! C0805BSM ! ; C16
C508_3 ! C508_3 ! ; C17
CE3580 ! CE3580 ! ; C18
CE3580 ! CE3580 ! ; C19
C508_5 ! C508_5 ! ; C20
CC509_5 ! CC509_5 ! ; C21
C10013_4 ! C10013_4 ! ; C22
C0805BSM ! C0805BSM ! ; C23
C0805BSM ! C0805BSM ! ; C24
C0805BSM ! C0805BSM ! ; C25
C0805BSM ! C0805BSM ! ; C26
C0805BSM ! C0805BSM ! ; C27
CC509_5 ! CC509_5 ! ; C28
CE3580 ! CE3580 ! ; C29
CE3580 ! CE3580 ! ; C30
C0805BSM ! C0805BSM ! ; C31
CE3580 ! CE3580 ! ; C32
C0805BSM ! C0805BSM ! ; C33
C508_5 ! C508_5 ! ; C34
C508_3 ! C508_3 ! ; C35
C0805BSM ! C0805BSM ! ; C36
C0805BSM ! C0805BSM ! ; C37
C0805BSM ! C0805BSM ! ; C38
C0805BSM ! C0805BSM ! ; C39
CE3580 ! CE3580 ! ; C40
CE3580 ! CE3580 ! ; C41
CE50130 ! CE50130 ! ; C42
C10013_4 ! C10013_4 ! ; C43
CE2050 ! CE2050 ! ; C44
C508_3 ! C508_3 ! ; C45
C508_5 ! C508_5 ! ; C46
Mon Dec 12 21:47:47 2022 Page 2
CC509_5 ! CC509_5 ! ; C47
C10013_5 ! C10013_5 ! ; C48
C10013_5 ! C10013_5 ! ; C49
C0805BSM ! C0805BSM ! ; C50
C0805BSM ! C0805BSM ! ; C51
C0805BSM ! C0805BSM ! ; C52
C0805BSM ! C0805BSM ! ; C53
C0805BSM ! C0805BSM ! ; C54
C0805BSM ! C0805BSM ! ; C55
C0805BSM ! C0805BSM ! ; C56
C0805BSM ! C0805BSM ! ; C57
C10013_5 ! C10013_5 ! ; C58
CE100350 ! CE100350 ! ; C59
C22527_9 ! C22527_9 ! ; C60
C10013_5 ! C10013_5 ! ; C61
C10013_5 ! C10013_5 ! ; C62
C10013_5 ! C10013_5 ! ; C63
CE100350 ! CE100350 ! ; C64
C10013_5 ! C10013_5 ! ; C65
CE3580 ! CE3580 ! ; C66
C0805BSM ! C0805BSM ! ; C67
CE3580 ! CE3580 ! ; C68
C22527_9 ! C22527_9 ! ; C69
C0805BSM ! C0805BSM ! ; C70
CE100350 ! CE100350 ! ; C71
C10013_5 ! C10013_5 ! ; C72
D41P2H-1 ! D41P2H-1 ! ; D1
D247P2 ! D247P2 ! ; D2
D4236P2 ! D4236P2 ! ; D3
D4236P2 ! D4236P2 ! ; D4
TRNPNBSM ! TRNPNBSM ! ; D5
D27P2H-1 ! D27P2H-1 ! ; D6
TRNPNBSM ! TRNPNBSM ! ; D7
TRNPNBSM ! TRNPNBSM ! ; D8
TRNPNBSM ! TRNPNBSM ! ; D9
D4236P2 ! D4236P2 ! ; D10
D4236P2 ! D4236P2 ! ; D11
D27P2H-1 ! D27P2H-1 ! ; D12
D41P2H-1 ! D41P2H-1 ! ; D13
D247P2 ! D247P2 ! ; D14
TRNPNBSM ! TRNPNBSM ! ; D15
D150 ! D150 ! ; D16
D150 ! D150 ! ; D17
D150 ! D150 ! ; D18
D150 ! D150 ! ; D19
D150 ! D150 ! ; D20
D150 ! D150 ! ; D21
D41P2H-1 ! D41P2H-1 ! ; D22
D150 ! D150 ! ; D23
D150 ! D150 ! ; D24
D150 ! D150 ! ; D25
D150 ! D150 ! ; D26
Mon Dec 12 21:47:47 2022 Page 3
D150 ! D150 ! ; D27
D150 ! D150 ! ; D28
Fuse 3A 125V ! Fuse 3A 125V ! ; F1
F3A1000VP4 ! F3A1000VP4 ! ; F2
FUSE5A350VAC ! FUSE5A350VAC ! ; F3
SIP-B1P2H ! SIP-B1P2H ! ; J1
SIP-B1P2 ! SIP-B1P2 ! ; J2
SIP-B1P2H ! SIP-B1P2H ! ; J3
SIP-B1P2H ! SIP-B1P2H ! ; J4
SIP-B1P6H ! SIP-B1P6H ! ; J5
SIP-B1P3H ! SIP-B1P3H ! ; J6
SIP-C3P3H ! SIP-C3P3H ! ; J7
L9P2 ! L9P2 ! ; L1
L9P2 ! L9P2 ! ; L2
L9P2 ! L9P2 ! ; L3
L9P2 ! L9P2 ! ; L4
L28_17.5P4 ! L28_17.5P4 ! ; L5
LED25C ! LED25C ! ; LED1
2SK2613 ! 2SK2613 ! ; Q1
2N4401 ! 2N4401 ! ; Q2
2N4403 ! 2N4403 ! ; Q3
2SK2613 ! 2SK2613 ! ; Q4
TRPNPBSM ! TRPNPBSM ! ; Q5
TRPNPBSM ! TRPNPBSM ! ; Q6
TRNPNBSM ! TRNPNBSM ! ; Q7
TRNPNBSM ! TRNPNBSM ! ; Q8
TRNPNBSM ! TRNPNBSM ! ; Q9
TRNPNBSM ! TRNPNBSM ! ; Q10
R100060 ! R100060 ! ; R1
R100060 ! R100060 ! ; R2
R100060 ! R100060 ! ; R3
R100060 ! R100060 ! ; R4
R1206NSM ! R1206NSM ! ; R5
R100060 ! R100060 ! ; R6
R1206NSM ! R1206NSM ! ; R7
R0805BSM ! R0805BSM ! ; R8
R0805BSM ! R0805BSM ! ; R9
R0805BSM ! R0805BSM ! ; R10
R100060 ! R100060 ! ; R11
R100060 ! R100060 ! ; R12
R1206NSM ! R1206NSM ! ; R13
R0805BSM ! R0805BSM ! ; R14
R100060 ! R100060 ! ; R15
R1206NSM ! R1206NSM ! ; R16
R0805BSM ! R0805BSM ! ; R17
R1206NSM ! R1206NSM ! ; R18
R100060 ! R100060 ! ; R19
R0805BSM ! R0805BSM ! ; R20
R1206NSM ! R1206NSM ! ; R21
R075005 ! R075005 ! ; R22
R1206NSM ! R1206NSM ! ; R23
R100060 ! R100060 ! ; R24
Mon Dec 12 21:47:47 2022 Page 4
R100060 ! R100060 ! ; R25
R0805BSM ! R0805BSM ! ; R26
R0805BSM ! R0805BSM ! ; R27
R075005 ! R075005 ! ; R28
R0805BSM ! R0805BSM ! ; R29
R075005 ! R075005 ! ; R30
R0805BSM ! R0805BSM ! ; R31
R0805BSM ! R0805BSM ! ; R32
R0805BSM ! R0805BSM ! ; R33
R075005 ! R075005 ! ; R34
R0805BSM ! R0805BSM ! ; R35
R0805BSM ! R0805BSM ! ; R36
R0805BSM ! R0805BSM ! ; R37
R0805BSM ! R0805BSM ! ; R38
R0805BSM ! R0805BSM ! ; R39
R0805BSM ! R0805BSM ! ; R40
R0805BSM ! R0805BSM ! ; R41
R0805BSM ! R0805BSM ! ; R42
R0805BSM ! R0805BSM ! ; R43
R0805BSM ! R0805BSM ! ; R44
R0805BSM ! R0805BSM ! ; R45
R0805BSM ! R0805BSM ! ; R46
R0805BSM ! R0805BSM ! ; R47
R0805BSM ! R0805BSM ! ; R48
R0805BSM ! R0805BSM ! ; R49
R0805BSM ! R0805BSM ! ; R50
R100060 ! R100060 ! ; R51
R100060 ! R100060 ! ; R52
R0805BSM ! R0805BSM ! ; R53
R0805BSM ! R0805BSM ! ; R54
R100060 ! R100060 ! ; R55
SC40 ! SC40 ! ; SC1
SC40 ! SC40 ! ; SC2
SC40 ! SC40 ! ; SC3
SC40 ! SC40 ! ; SC4
SC40 ! SC40 ! ; SC5
SC40 ! SC40 ! ; SC6
SRSQM1411 ! SRSQM1411 ! ; SR1
SRSQM1411 ! SRSQM1411 ! ; SR2
SRSQM1411 ! SRSQM1411 ! ; SR3
SRSQM1411 ! SRSQM1411 ! ; SR4
SRSQM1411 ! SRSQM1411 ! ; SR5
SRSQM1411 ! SRSQM1411 ! ; SR6
SRSQM130100 ! SRSQM130100 ! ; SR7
SRSQM130100 ! SRSQM130100 ! ; SR8
SRSQM130100 ! SRSQM130100 ! ; SR9
SRSQM130100 ! SRSQM130100 ! ; SR10
SRSQM130100 ! SRSQM130100 ! ; SR11
SRSQM130100 ! SRSQM130100 ! ; SR12
ER42 ! ER42 ! ; T1
EEL-16X ! EEL-16X ! ; T2
TEST ! TEST ! ; TP1
Mon Dec 12 21:47:47 2022 Page 5
TEST ! TEST ! ; TP2
TEST ! TEST ! ; TP3
TEST ! TEST ! ; TP4
TEST ! TEST ! ; TP5
TEST ! TEST ! ; TP6
TEST ! TEST ! ; TP7
TEST ! TEST ! ; TP8
TEST ! TEST ! ; TP9
TEST ! TEST ! ; TP10
TEST ! TEST ! ; TP11
TEST ! TEST ! ; TP12
TEST ! TEST ! ; TP13
TEST ! TEST ! ; TP14
TEST ! TEST ! ; TP15
TEST ! TEST ! ; TP16
TEST ! TEST ! ; TP17
TEST ! TEST ! ; TP18
TEST ! TEST ! ; TP19
TEST ! TEST ! ; TP20
TEST ! TEST ! ; TP21
TEST ! TEST ! ; TP22
2844 ! 2844 ! ; U1
PH521 ! PH521 ! ; U2
AZ431LS23TSM ! AZ431LS23TSM ! ; U3
AZ431LS23TSM ! AZ431LS23TSM ! ; U4
AZ431LS23TSM ! AZ431LS23TSM ! ; U5
AZ431LS23TSM ! AZ431LS23TSM ! ; U6
7805SM ! 7805SM ! ; U7
D41P2H-1 ! D41P2H-1 ! ; VD1
D41P2H-1 ! D41P2H-1 ! ; VD2
D41P2H-1 ! D41P2H-1 ! ; VD3
D41P2H-1 ! D41P2H-1 ! ; VD4
D41P2H-1 ! D41P2H-1 ! ; VD5
D41P2H-1 ! D41P2H-1 ! ; VD6
D41P2H-1 ! D41P2H-1 ! ; VD7
_NETS
Vfb; C38.1 C42.1 C50.2 D14.1 L4.1,
R25.1 R26.1 R29.1 R31.1 TP16.1,
VDC; C48.1 C58.1 C59.1 D3.1 D4.2,
L5.3 Q1.2 R1.1 R28.1 R51.2,
SR1.2 SR2.2 SR3.2 TP19.1
VCC-15V; C30.2 C32.2 C33.2 C34.1 C35.1,
C36.2 C37.2 J5.3 L3.2 R19.2,
VCC+18V; C2.1 C4.2 C44.1 D1.1 Q2.1,
Q6.2 R18.1 R21.1 R23.1 R27.2,
R32.1 TP1.1 U1.7 VD1.1 VD6.1,
VCC+15V; C36.1 C37.1 C39.1 C40.1 C41.1,
C45.2 C46.2 C68.1 C70.2 D22.1,
J5.4 J5.5 L4.2 R24.1 R40.1,
Mon Dec 12 21:47:47 2022 Page 6
R43.1 R45.1 R54.1 TP15.1 U7.1,
VCC+12V; C16.2 C17.1 C19.1 C20.1 J7.3,
L2.2 R12.2 TP5.1
VCC+5V; C52.1 C66.1 C67.2 D22.2 J2.2,
LED1.2 R38.1 R39.1 R53.1 TP21.1,
U7.3
PWR_NG; J5.6 Q9.3 R38.2 TP17.1
PE; C5.2 C14.2 C43.1 C61.2 C65.1,
SC1.1 SC2.1 SC3.1 SC4.1 SC5.1,
SC6.1
NetVD4_1; VD4.1 VD5.1
NetVD2_1; VD2.1 VD3.1
NetR45_2; R45.2 R46.2 U6.2 VD7.1
NetR40_2; R40.2 R47.1
NetR35_1; R35.1 VD6.2
NetR31_2; R31.2 R36.1 R41.1 U4.1
NetR30_1; R30.1 R34.1
NetR28_2; R28.2 R30.2
NetR26_2; R26.2 U2.1
NetR13_1; R13.1 R16.1 T2.10
NetR5_1; R5.1 R7.1 T2.6
NetR2_1; R2.1 R3.1
NetR1_2; R1.2 R2.2
NetQ9_1; Q9.1 Q10.3 R39.2
NetQ7_1; Q7.1 R37.2
NetQ6_3; Q6.3 R37.1
NetQ6_1; Q6.1 R32.2 U3.2
NetQ5_2; Q5.2 R27.1 R33.1
NetQ2_2; Q2.2 Q3.2 TP7.1 U1.6
NetLED1_1; LED1.1 R46.1
NetF3_1; F3.1 J6.1
NetF2_1; F2.1 J1.1 J1.2
NetD27_2; D27.2 J3.1 J3.2
NetD27_1; D27.1 D28.2
NetD25_1; D25.1 D26.1 D28.1 SR10.1 SR11.1,
SR12.1
NetD24_1; D24.1 D26.2
NetD23_1; D23.1 D25.2
NetD21_1; D21.1 D24.2 J6.3
NetD20_1; D20.1 D23.2 F3.2
NetD19_1; D19.1 D21.2
NetD18_1; D18.1 D20.2
NetD17_2; D17.2 D18.2 D19.2 SR7.1 SR8.1,
SR9.1
NetD16_2; D16.2 D17.1
NetD16_1; D16.1 F2.3 F2.4
NetD15_3; D15.3 Q5.1 Q8.3 R33.2
NetD13_2; D13.2 T1.8
NetD13_1; D13.1 R18.2 R21.2 R23.2
NetD9_3; D9.3 R10.2
NetD8_3; D8.3 R13.2
Mon Dec 12 21:47:47 2022 Page 7
NetD8_1; D8.1 D8.2 Q4.1 R16.2 R17.1,
VD4.2
NetD5_3; D5.3 R5.2
NetD5_1; D5.1 D5.2 Q1.1 R7.2 R9.1,
VD2.2
NetD3_2; D3.2 D11.2 Q4.2 SR4.2 SR5.2,
SR6.2 T1.5 TP10.1
NetD1_2; D1.2 R3.2
NetC69_2; C69.2 L5.1 SR10.2 SR11.2 SR12.2,
NetC65_2; C65.2 C72.1
NetC64_2; C64.2 C71.1 R52.1 R55.1
NetC62_2; C62.2 C63.1
NetC60_2; C60.2 C69.1
NetC60_1; C60.1 L5.4 SR7.2 SR8.2 SR9.2,
NetC59_2; C59.2 C64.1 R51.1 R52.2
NetC58_2; C58.2 C61.1
NetC57_2; C57.2 R47.2 R49.1 U5.1
NetC56_2; C56.2 R43.2 R50.1 U5.2 U6.1,
NetC55_2; C55.2 Q10.1 R48.1 VD7.2
NetC54_2; C54.2 Q5.3 Q8.1 R35.2 R42.1,
NetC53_2; C53.2 R34.2 R44.1 U3.1
NetC51_2; C51.2 R29.2 U2.2 U4.2
NetC51_1; C51.1 R36.2
NetC48_2; C48.2 C49.1
NetC47_2; C47.2 R25.2
NetC47_1; C47.1 C49.2 D14.2 T1.10
NetC29_2; C29.2 C31.2 D12.2 L3.1 R15.1,
NetC28_2; C28.2 D11.1 SR4.1 SR5.1 SR6.1,
NetC28_1; C28.1 Q4.3 R17.2 R20.2 R22.1,
T2.9 VD5.2
NetC27_1; C27.1 R20.1 TP11.1 U1.3
NetC26_2; C26.2 D7.3 R14.1
NetC25_2; C25.2 D7.2 R8.1 R14.2 U1.8,
NetC24_1; C24.1 R8.2 TP8.1 U1.4
NetC21_2; C21.2 R15.2
NetC21_1; C21.1 D12.1 T1.12
NetC15_2; C15.2 C18.1 D6.1 L2.1 R11.2,
NetC13_2; C13.2 R11.1
NetC13_1; C13.1 D6.2 T1.14
NetC12_2; C12.2 D4.1 SR1.1 SR2.1 SR3.1,
NetC12_1; C12.1 D10.1 Q1.3 R9.2 T1.1,
T2.5 TP3.1 VD3.2
NetC11_2; C11.2 Q2.3 Q3.3 R10.1
Mon Dec 12 21:47:47 2022 Page 8
NetC11_1; C11.1 T2.4
NetC7_2; C7.2 C8.1 C9.1 C10.1 F1.1,
L1.2 R6.2 TP2.1
NetC3_1; C3.1 C6.2 D2.1 L1.1 R4.2,
NetC1_2; C1.2 R4.1
NetC1_1; C1.1 D2.2 T1.18
MON+15V; F1.2 J4.2
MON GND; C3.2 C5.1 C6.1 C7.1 C8.2,
C9.2 C10.2 J4.1 R6.1 T1.17,
TP4.1
GND+15V; C22.2 C29.1 C30.1 C31.1 C32.1,
C33.1 C34.2 C35.2 C38.2 C39.2,
C40.2 C41.2 C42.2 C43.2 C45.1,
C46.1 C50.1 C52.2 C55.1 C56.1,
C57.1 C63.2 C66.2 C67.1 C68.2,
C70.1 J2.1 J5.1 J5.2 Q9.2,
Q10.2 R19.1 R24.2 R41.2 R48.2,
R49.2 R50.2 R53.2 R54.2 T1.11,
TP12.1 TP18.1 TP20.1 U4.3 U5.3,
U6.3 U7.2
GND+12V; C14.1 C15.1 C16.1 C17.2 C18.2,
C19.2 C20.2 C22.1 J7.1 R12.1,
T1.13 TP9.1
GND; C2.2 C4.1 C23.1 C24.2 C25.1,
C26.1 C27.2 C44.2 C53.1 C54.1,
C62.1 C71.2 C72.2 D9.1 D9.2,
D10.2 L5.2 Q3.1 Q7.2 Q8.2,
R22.2 R42.2 R44.2 R55.2 T1.9,
T2.2 TP13.1 TP14.1 TP22.1 U1.2,
U1.5 U2.3 U3.3 VD1.2
2844cmp; C23.2 D7.1 D15.1 D15.2 Q7.3,
TP6.1 U1.1 U2.4
_END
===========================================================
Starting gate assignment. Mon Dec 12 21:47:47 2022
Assigning gates of drawing high voltage switching power.brd
Gates of differing rooms will not be assigned to the same component.
Gate assignment will use empty slots in existing components.
STEP I
STEP II
Finished with gate assignment. Mon Dec 12 21:47:47 2022
===========================================================
===========================================================
End of NETLIST IN Syntax/Logic Check
===========================================================
Total Netlist Warnings = 0.
Total Netlist Errors = 0.
===========================================================
Total Device File Warnings = 0.
Total Device File Errors = 0.
===========================================================
Total Combined Netlist and Device File Warnings = 0.
Total Combined Netlist and Device File Errors = 0.
Mon Dec 12 21:47:47 2022 Page 9
===========================================================
End of Allegro NETLIST IN Log
===========================================================
WARNIING: The STEP mapping file search path 'STEP_MAPPING_PATH' was not set.
============= End of Device->STEP Mapping =============
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