高通qcc3034芯片datasheet与原理图

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Switch mode regulators
- }( O  p7 K9 Q5 Y; d: R5 ?QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
# A1 P2 Y0 U% f) Preceive power from VBAT or VCHG under application software control.
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
VFBGA and the flash memory. The System SMPS can supply power to external components.
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
The SMPS both have three operating modes:
/ f) j/ z' P; i/ f" Q■ Normal (PWM)
■ Two low-power modes with reduced current capability:
; f+ u- U9 y1 y; j% ?1 q$ ]! V+ u□ PFM
8 V& Z( b6 j# R1 y, i, c  O) I□ ULP
Normally the system auto switches, but this is optionally disabled.
" G  _7 W2 H! y/ O. a8 |7 dThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
5 J- [9 X+ @5 W) t$ WFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
6 a- D" K. i" s2 f; \/ hCH285-1).
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
6 @0 y( a/ D. |' [# p% L$ uThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
0 p# ~3 k; C" v/ G

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