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Loading... E:\allegroXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat( Q# @4 S. I& J2 y5 j4 m4 z6 ]1 w" J
7 P6 S9 o# k. O2 \: ^9 e+ oLoading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat: O* B& l, R# F. Q$ g
" y4 v$ Y3 c9 J% X/ o' SLoading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat
1 e0 o/ ?6 d9 J! g#77 ERROR(SPCODD-77): Could not open file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat.
: e7 t3 ^: ?% i9 K* BYou might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.
0 V( p: r8 o4 a4 q' wERROR(SPCODD-382): Error at line 1 in file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat. Error loading the parts list file" J+ u" f3 V# K+ h* d# s, I% M
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#292 ERROR(ORCAP-36026): Unable to read logical netlist data.
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' D+ I2 L& j$ `* m$ {' Y( M8 Xorcad在导网表时出现打不开pstxprt.dat文件,在Allegro文件下不能找到该文件,不知道为什么没有生成,恳请大佬帮助一下。9 O( a& q7 z; j) M
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