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发表于 2023-4-3 18:30:57
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Switch mode regulators
: b2 P& n" T: j" yQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
3 {' \4 N3 D8 Qreceive power from VBAT or VCHG under application software control.3 Q _; C/ t5 N! {9 Q* G% G3 R& ?8 A
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040: H' }* y/ _1 D' q" k4 R/ w
VFBGA and the flash memory. The System SMPS can supply power to external components.1 H* h+ c3 h9 ]( d
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches& f+ S3 e& E: c# U! V
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.5 \4 M- U% v) Q: [, G
The SMPS both have three operating modes:% T- y- p: j; L% t
■ Normal (PWM)
m5 g' m) K; W0 b, w■ Two low-power modes with reduced current capability:
8 d" g& L! x2 [# f, _□ PFM
4 ?4 i: c! r- j: x□ ULP
) V& C$ X1 C- {4 w* ENormally the system auto switches, but this is optionally disabled.
G& V# m3 M5 `# c9 r8 J a% fThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.9 T! Q, Z7 @, r) Z4 F3 n
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-3 }8 m% I( |5 m% ^2 ` \
CH285-1).
J3 y a' ~7 ^8 x! u4 CA single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have: o0 |0 W( M' S: `
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
V4 M7 e$ r! `, UThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
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